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Chapter 2 - Hardware Installation
38
Table 2-14. Secondary Base Address For 512 Byte Short I/O (Continued)
NOTE: 0 = IN (Logical 0), F = OUT (Logical 1)
ADDRESS J23 PIN SETTINGS J24,J25,J26 PIN SETTINGS
15-16 13-14 11-12 9-10 7-8 5-6 3-4 1-2 J24 J25 J26
5000 F 0 0 0 F 0 F 0 F 0 0
5200 F F 0 0 F 0 F 0 F 0 0
5400 F 0 F 0 F 0 F 0 F 0 0
5600 F F F 0 F 0 F 0 F 0 0
5800 F 0 0 F F 0 F 0 F 0 0
5A00 FF0FF0 F0 F 0 0
5C00 F 0 F F F 0 F 0 F 0 0
5E00 F F F F F 0 F 0 F 0 0
6000 F 0 0 0 0 F F 0 F 0 0
6200 F F 0 0 0 F F 0 F 0 0
6400 F 0 F 0 0 F F 0 F 0 0
6600 F F F 0 0 F F 0 F 0 0
6800 F 0 0 F 0 F F 0 F 0 0
6A00 F F 0 F 0 F F 0 F 0 0
6C00 F 0 F F 0 F F 0 F 0 0
6E00 F F F F 0 F F 0 F 0 0
7000 F 0 0 0 F F F 0 F 0 0
7200 F F 0 0 F F F 0 F 0 0
7400 F 0 F 0 F F F 0 F 0 0
7600 F F F 0 F F F 0 F 0 0
7800 F 0 0 F F F F 0 F 0 0
7A00 F F 0 F F F F 0 F 0 0
7C00 F 0 F F F F F 0 F 0 0
7E00 F F F F F F F 0 F 0 0
8000 F 0 0 0 0 0 0 F F 0 0
8200 F F 0 0 0 0 0 F F 0 0
8400 F 0 F 0 0 0 0 F F 0 0
8600 F F F 0 0 0 0 F F 0 0
8800 F 0 0 F 0 0 0 F F 0 0
8A00 F F 0 F 0 0 0 F F 0 0
8C00 F 0 F F 0 0 0 F F 0 0
8E00 F F F F 0 0 0 F F 0 0
9000 F 0 0 0 F 0 0 F F 0 0
9200 F F 0 0 F 0 0 F F 0 0
9400 F 0 F 0 F 0 0 F F 0 0
9600 F F F 0 F 0 0 F F 0 0
9800 F 0 0 F F 0 0 F F 0 0
9A00 F F 0 F F 0 0 F F 0 0
9C00 F 0 F F F 0 0 F F 0 0
9E00 F F F F F 0 0 F F 0 0
- V/Ethernet 4221 Condor 1
- User’s Guide 1
- Copyright Notice 3
- Disclaimer 3
- For Assistance 4
- Trademark Acknowledgments 4
- TABLE OF CONTENTS 5
- LIST OF FIGURES 9
- LIST OF TABLES 11
- CHAPTER 1 13
- INTRODUCTION 13
- Conventions 14
- General Description 14
- Features 14
- Physical Description 15
- Functional Description 15
- VMEbus Master Interface 16
- Local Bus 16
- VMEbus Short I/O Interface 17
- CPU Core 17
- CPU/LBUS Interface 18
- CHAPTER 2 19
- HARDWARE INSTALLATION 19
- OPTIONAL 21
- DAUGHTER 21
- Step 1. Visual Inspection 26
- Diagnostic LEDs 26
- Board Status LEDs 27
- Motherboard Jumper Settings 28
- J12 VME Bus Grant: 29
- J13 Firmware Option Jumpers: 29
- J14 Firmware Option Jumpers: 30
- Step 5. Power Off System 63
- Step 6. Cabling Procedure 63
- RS232 Connectors And Cables 64
- CHAPTER 3 65
- MACSI HOST INTERFACE 65
- Field Offset 66
- Contiguous Data Allocation 66
- System Interface 67
- MACSI Organization 67
- Master Status Register (MSR) 69
- 1514131211109876543210 69
- Master Control Register (MCR) 70
- Onboard Command Queue Entry 71
- Offboard Command Queue Entry 72
- DMA Transfer Control Word 73
- Host Address 73
- Offboard Transfer Length 73
- Work Queue Number 73
- Command Response Block (CRB) 74
- Command Tag 75
- IOPB Length 75
- Transfer Count 76
- Product Code 77
- Product Variation 77
- Firmware Revision Level 78
- Firmware Revision Date 78
- Controller Statistics Block 79
- Transmit Commands Submitted 80
- Transmit DMA Completions 80
- Transmit 82596 Completions 80
- Successful Transmits 80
- Failed Transmits 80
- IO Parameter Blocks (IOPBs) 82
- Common IOPB Structures 82
- Initialize Controller 85
- Number of CQE Entries 86
- Interrupt Levels and Vectors 87
- DMA Burst Count 87
- Special Network Options 87
- Offboard CRB host address 88
- MAC Control/Status 89
- Transfer size 92
- MAC status/control 92
- MAC returned information 96
- Change Default Node Address 97
- Transmit 99
- Transmit -- In-Line Gathers 100
- Number of Elements 101
- Total transfer count 101
- Element transfer count 101
- Buffer address 101
- Receive 102
- Command Options 103
- Buffer Address 103
- Packet Type / Length Field 103
- Command Code 103
- Source Address 104
- Report Network Statistics 107
- Return Status 108
- Host Memory Buffer Address 108
- Max Transfer Size 108
- Timer Interval 108
- Network Statistics Block 109
- APPENDIX A 111
- SPECIFICATIONS 111
- Mechanical (Nominal) 112
- Operating Environment 112
- Reliability 112
- APPENDIX B 113
- CONNECTOR PINOUTS AND CABLING 113
- VMEbus Connectors 114
- 10BaseT Connector Signals 116
- AUI Connector Signals 117
- RS232 Connector and Cable 118
- APPENDIX C 119
- ERROR CODES 119
- Appendix B 120
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