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Initialize Multiple Completions
93
Initialize Multiple Completions
This command enables the controller to return multiple completed commands to the host with a single completion via
the Command Response Block, with a single (optional) interrupt.
When commands are completed using this mechanism, the returned IOPB is replaced with a substantially different
Multiple Completion Returned Command structure. Please refer to the system interface section of this chapter for
details.
Once the host has enabled multiple completions, the controller will still post back individually completed commands,
for any of the following conditions:
Only a single command required posting back (the multiple completion mechanism will never be used to post
back less than two commands)
The Disable Multiple Completion bit is set in a particular Transmit or Receive IOPB
The IOPB completed with error or exception. Such IOPBs will always be returned from the controller to the
host as a single completion.
When posting a group of commands as a multiple completion, the controller will ignore all interrupt related
information in the individual IOPBs, including the Interrupt Enable bit in the Command Options word, and the
interrupt level and vector, and will use the related fields provided in the Initialize Multiple Completions instead.
However, commands returned via the single completion mechanism will always use the interrupt information
contained in the individual IOPB.
The Initialize Multiple Completion IOPB must be issued through the Master Command Entry.
Table 3-34. Common IOPB Structures
Command Code
This field must be set to 0x80 to execute the Initialize Multiple Completions command.
Common IOPB Structures
Offst 1514131211109876543210
0x00 Command Code
0x01 Command Options
0x02 Return Status
0x03 Normal Completion Level Normal Completion Vector
0x04 Error Completion Level Error Completion Vector
0x05 Reserved
0x06 Control Flags
0x07 Group Interrupt Level Group Interrupt Vector
0x08 Minimum Group Count
0x09 Maximum Group Count
- V/Ethernet 4221 Condor 1
- User’s Guide 1
- Copyright Notice 3
- Disclaimer 3
- For Assistance 4
- Trademark Acknowledgments 4
- TABLE OF CONTENTS 5
- LIST OF FIGURES 9
- LIST OF TABLES 11
- CHAPTER 1 13
- INTRODUCTION 13
- Conventions 14
- General Description 14
- Features 14
- Physical Description 15
- Functional Description 15
- VMEbus Master Interface 16
- Local Bus 16
- VMEbus Short I/O Interface 17
- CPU Core 17
- CPU/LBUS Interface 18
- CHAPTER 2 19
- HARDWARE INSTALLATION 19
- OPTIONAL 21
- DAUGHTER 21
- Step 1. Visual Inspection 26
- Diagnostic LEDs 26
- Board Status LEDs 27
- Motherboard Jumper Settings 28
- J12 VME Bus Grant: 29
- J13 Firmware Option Jumpers: 29
- J14 Firmware Option Jumpers: 30
- Step 5. Power Off System 63
- Step 6. Cabling Procedure 63
- RS232 Connectors And Cables 64
- CHAPTER 3 65
- MACSI HOST INTERFACE 65
- Field Offset 66
- Contiguous Data Allocation 66
- System Interface 67
- MACSI Organization 67
- Master Status Register (MSR) 69
- 1514131211109876543210 69
- Master Control Register (MCR) 70
- Onboard Command Queue Entry 71
- Offboard Command Queue Entry 72
- DMA Transfer Control Word 73
- Host Address 73
- Offboard Transfer Length 73
- Work Queue Number 73
- Command Response Block (CRB) 74
- Command Tag 75
- IOPB Length 75
- Transfer Count 76
- Product Code 77
- Product Variation 77
- Firmware Revision Level 78
- Firmware Revision Date 78
- Controller Statistics Block 79
- Transmit Commands Submitted 80
- Transmit DMA Completions 80
- Transmit 82596 Completions 80
- Successful Transmits 80
- Failed Transmits 80
- IO Parameter Blocks (IOPBs) 82
- Common IOPB Structures 82
- Initialize Controller 85
- Number of CQE Entries 86
- Interrupt Levels and Vectors 87
- DMA Burst Count 87
- Special Network Options 87
- Offboard CRB host address 88
- MAC Control/Status 89
- Transfer size 92
- MAC status/control 92
- MAC returned information 96
- Change Default Node Address 97
- Transmit 99
- Transmit -- In-Line Gathers 100
- Number of Elements 101
- Total transfer count 101
- Element transfer count 101
- Buffer address 101
- Receive 102
- Command Options 103
- Buffer Address 103
- Packet Type / Length Field 103
- Command Code 103
- Source Address 104
- Report Network Statistics 107
- Return Status 108
- Host Memory Buffer Address 108
- Max Transfer Size 108
- Timer Interval 108
- Network Statistics Block 109
- APPENDIX A 111
- SPECIFICATIONS 111
- Mechanical (Nominal) 112
- Operating Environment 112
- Reliability 112
- APPENDIX B 113
- CONNECTOR PINOUTS AND CABLING 113
- VMEbus Connectors 114
- 10BaseT Connector Signals 116
- AUI Connector Signals 117
- RS232 Connector and Cable 118
- APPENDIX C 119
- ERROR CODES 119
- Appendix B 120
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